A hierarchical depth buffer for minimizing memory bandwidth in 3D rendering engine: Depth Filter

نویسندگان

  • Chang-Hyo Yu
  • Lee-Sup Kim
چکیده

In this paper, we propose a new class of hierarchical depth test which saves memory bandwidth in 3D graphics rendering engine by reducing the number of pixels being passed to the per-pixel operation pipeline. This new filtering, Depth Filter, can be implemented by adding a simple hardware in front of the perpixel operation pipeline. m e Depth Filter is a filtering block which decides whether a pixel is shaded by celiain plane. The plane is the mask which has the history that a pixel has appeared in front of the plane. If the pixel is shaded, the pixel can be removed. The simulation shows that Depth Filter reduces the number of pixels to the next stage up to 62.1 percent in random scene. As a result, 62.1% of memory bandwidth is saved with simple extra hardware.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors

As a 3D scene becomes increasingly complex and the screen resolution increases, the design of an effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture that performs the depth test twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste due to fetching unnecessary o...

متن کامل

A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors

As a 3D scene becomes increasingly complex and the screen resolution increases, the design of effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture, which performs a depth test operation twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste caused by fetching unn...

متن کامل

A 7.1-GB/s Low-Power Rendering Engine in 2-D Array-Embedded Memory Logic CMOS for Portable Multimedia System

A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping...

متن کامل

Camera Arrangement in Visual 3D Systems using Iso-disparity Model to Enhance Depth Estimation Accuracy

In this paper we address the problem of automatic arrangement of cameras in a 3D system to enhance the performance of depth acquisition procedure. Lacking ground truth or a priori information, a measure of uncertainty is required to assess the quality of reconstruction. The mathematical model of iso-disparity surfaces provides an efficient way to estimate the depth estimation uncertainty which ...

متن کامل

A Framework for Sample-Based Rendering with 0-Buffers

We present an innovative modeling and rendering primitive, called the 0-buffer. for sample-based graphics, such as images, volumes, and points. The 2D or 3D 0-buffer is in essence a conventional image or a volume, respectively, except that samples are not restricted to a regular grid. A sample position in the 0-buffer is recorded as an offset to the nearest grid point of a regular base grid (he...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2003